This application is related to the following co-pending, commonly assigned applications which are incorporated by reference:
U.S. patent application Ser. No. 09/028,249 entitled xe2x80x9cVERTICAL BIPOLAR READ ACCESS FOR LOW VOLTAGE MEMORY CELL,xe2x80x9d
U.S. patent application Ser. No. 08/944,312 entitled xe2x80x9cCIRCUIT AND METHOD FOR A FOLDED BIT LINE MEMORY USING TRENCH PLATE CAPACITOR CELLS WITH BODY BIAS CONTACTS,xe2x80x9d
U.S. patent application Ser. No. 08/939,732, entitled xe2x80x9cCIRCUIT AND METHOD FOR AN OPEN BIT LINE MEMORY CELL WITH A VERTICAL TRANSISTOR AND TRENCH PLATE TRENCH CAPACITORxe2x80x9d
U.S. patent application Ser. No. 08/939,742, entitled xe2x80x9cCIRCUIT AND METHOD FOR A FOLDED BIT LINE MEMORY CELL WITH VERTICAL TRANSISTOR AND TRENCH CAPACITOR,xe2x80x9d and
U.S. patent application Ser. No. 08/944,890, entitled xe2x80x9cCIRCUIT AND METHOD FOR AN OPEN BIT LINE MEMORY CELL WITH A VERTICAL TRANSISTOR AND TRENCH PLATE TRENCH CAPACITOR.xe2x80x9d
The present invention relates generally to integrated circuits and in particular the present invention relates to integrated circuit memory devices.
Complimentary metal oxide semiconductor field effect transistors (CMOS FETs) are prevalent in integrated circuit technology because they generally demand less power than bipolar transistors. Threshold voltage variations of CMOS transistors, however, are beginning to pose impractical limitations on CMOS devices as power supply voltages are reduced. In a 0.2 micron CMOS technology a 0.4 V distribution in threshold voltages might be anticipated. With a one volt power supply, this distribution can cause large variations in the speed of a logic circuit, such as those used in integrated memory circuits. For example, a threshold voltage of 0.6 V is required in a DRAM memory cell access transistor to insure low sub-threshold voltage leakage currents. If a threshold voltage distribution of 0.4 volts is experienced, there will be instances where little or no excess voltage above threshold voltage is available. As such, data transfer from a memory cell via such a transistor will be very slow.
A basic problem with CMOS access transistors results from the fact that CMOS devices do not function well at low voltages and require the use of higher than desirable power supply voltages, currently around two volts in 0.2 micron CMOS technology. Various techniques have been proposed to compensate for this in CMOS technology. For example, some form of transistor forward body bias, or specialized circuits to compensate for threshold voltage variations can be used.
Various types of lateral MOS transistors have been described and utilized in CMOS technology. Lateral bipolar transistors have received renewed interest with the advent of bipolar complementary metal oxide semiconductor (BiCMOS) technologies.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an access device for use in a low voltage memory device which performs fast read access of memory data.
The above mentioned problems with integrated circuit memory devices and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A memory cell access device is described which uses a combination of bipolar junction and CMOS transistors as access devices to store and read data on a trench plate trench capacitor.
In particular, one embodiment of the present invention provides a memory cell access device that has two access transistors. The first access transistor is an n-channel field effect transistor (FET) that is coupled between a trench plate trench capacitor and a data communication line. The second access transistor is an NPN bipolar junction transistor that is coupled between the trench plate trench capacitor and the data communication line. The n-channel access transistor and the NPN bipolar junction transistor are connected in parallel, and a base connection of the NPN bipolar junction transistor is coupled to a body of the n-channel field effect transistor.
In another embodiment, a low voltage memory cell access device fabricated as a vertical pillar structure is provided. The memory cell access device includes a field effect transistor that is coupled between a trench plate trench capacitor and a data communication line. The memory cell access device also includes a bipolar junction transistor that is coupled between the memory cell and the data communication line. The field effect transistor and the bipolar junction transistor are connected in parallel, with a base connection of the bipolar junction transistor that is coupled to a body of the field effect transistor.
In another embodiment, a memory device having a low voltage supply is provided. The memory device comprises a plurality of memory cells, a plurality of data communication bit lines, and a plurality of memory cell access devices coupled between the plurality of memory cells and the plurality of data communication bit lines. Each of the plurality of memory cell access devices comprises a field effect transistor and a bipolar junction transistor. The field effect transistor and the bipolar junction transistor are connected in parallel between a trench plate trench capacitor and a data communication bit line.
In another embodiment, a method of accessing a memory cell is provided. The method includes activating a field effect transistor coupled between a trench plate trench capacitor and a data communication line for writing data to the memory cell, and activating a bipolar junction transistor coupled between the trench plate trench capacitor and a data communication line for reading a charge stored on the memory cell.